Integrated circuits conventionally comprise a substrate, semiconductor devices, and wiring (e.g., metallization) layers formed above the semiconductor devices. The wiring layers comprise various interconnects that provide electrical connections between the devices and external connections. Solder projections (also referred to as solder bumps, bumps, or solder balls) are commonly utilized to provide a connection between the last (e.g., top) wiring level of a semiconductor device and another device. A common type of solder bump is the controlled collapse chip connection (C4) solder bump.
Current generation chip products make use of an aluminum last-metal (LM) pad which connects to a C4 solder bump. There are two primary variations on this structure. On the one hand, in structures used specifically for base silicon-on-insulator (SOI) technologies, the aluminum level comprises only a pad (i.e., no wires or other structures), the pad making a connection directly down through a large, centrally located via opening to the last metal wiring level (e.g., wire, interconnect, etc.). On the other hand, in conventional structures used for foundry and application specific integrated circuit (ASIC) technologies, the aluminum level comprises a combination pad and aluminum last-metal wiring level. The pad in the latter case makes contact to the last metal wiring level through multiple small vias, which are offset in location with respect to the pad center (e.g., by about 10 μm). However, in both instances, the pad contacts the ball limiting metallization (BLM) layer (also known as the under bump metallization, i.e., UBM) in a single large contact area.
As dimensions of features (e.g., pads, wires, interconnects, vias, etc.) continue to shrink to create smaller devices, the maximum allowable current density decreases rapidly due to electromigration (EM) effects. Electromigration is a well known phenomenon in which, generally speaking, atoms of a metal feature are displaced due to the electrical current passing through the feature. The migration of atoms can result in voids in the feature, which can increase electrical resistance or cause failure of the feature, both of which negatively impact reliability of the integrated circuit. For example, in C4 solder bump contact arrangements, electromigration damage typically originates at a location of highest current density and then progresses across the interface between the solder bump and the BLM until the connection is broken.
For conventional technologies, C4 solder bump electromigration performance is approaching a performance limit, especially as the technologies migrate to lead-free C4 solder structures that are more susceptible to electromigration. In conventional C4 solder bump contact designs, the electrical current pools (e.g., becomes crowded), which results in a localized increase in current density. For example, in the known pad arrangements discussed above, current tends to pool at a small area of the leading edge of the connection between the wire, pad, BLM, and solder bump. Particularly, in many applications, nearly all of the current flows through a narrow region at the leading edge of the via, and very little current flows through the remainder of the via. This crowding of current associated with C4 pad and/or via structures often results in electromigration void formation, which can lead to increased resistance and ultimately failure of the device.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.